1. Field of the Invention
The present invention relates to computer systems with a system ROM including a serial-access PROM coupled to an auto-configuring memory controller for shadowing BIOS code from the serial-access PROM.
2. Description of the Related Art
Today's modern personal computer system is typically initialized, or boot-strapped, during a power-up sequence using system software also known as firmware and information representing a sequence of internal control variables stored within a system read-only-memory (ROM). Since the system ROM is non-volatile, the content of the ROM contains valid data or instructions so that the computer system can be reliably boot-strapped to a point where the disk operating system (DOS) can be loaded to complete the boot-up sequence.
In an IBM PC or an IBM compatible PC system, the system ROM stores the basic input/output system (BIOS) which is executed upon power-up by the microprocessor to initialize the system, to perform a power-on-self-test (POST), and to provide certain low level, hardware dependent support for the display, floppy/hard disk drives, and communication devices. BIOS code provides the lowest level of interface between the operating system and the hardware. In the original PC architecture, the BIOS code was fairly straightforward and required little memory space. However, more sophisticated routines and data have more recently been included in the system ROM, based upon the needs and complexity of a given computer system.
In addition to the microprocessor which may be used as a central processing unit (CPU), other processing devices are also present in a modern computer. These processing devices can be a coprocessor for performing specialized processing, a digital signal processor for handling modem, video and signal processing requirements, and one or more microcontrollers which handle the peripheral devices and offload the processing from the microprocessor. These processing devices may also require one or more ROMs to store their operating code. Typically, a microcontroller has a small amount of on-chip ROM and RAM to enable the microcontroller to operate with a minimum part count. However, certain applications require more storage space than available with the built-in ROM on the microcontroller. In these instances, the microcontroller may require an external ROM device to handle more sophisticated applications of software.
A large capacity, reprogrammable storage device called a flash ROM is typically used to store the POST and BIOS routines required for the initialization and operation of the computer system. While most memory technologies have densities that are increasing, flash memory technology has enabled flash ROM to achieve even higher densities providing large memory capacity in smaller packages. These higher densities in smaller packages have led to increases in the minimum memory capacity of flash ROM that is available on the market. Cost of flash ROM has, however, remained relatively high based on memory capacity rather than package size.
Presently, there are ongoing initiatives to dramatically reduce BIOS code in size by decreasing the run-time support that has traditionally been present in BIOS. While a conventional BIOS image typically exceeds 128 KB, an advanced BIOS image lacking run-time support services would be well serviced with 32 KB. The use of relatively expensive flash ROM with its increased densities as system ROM thus is no longer desirable or cost-efficient. While today's flash ROMs have a minimum size of 128 KB, BIOS without run-time services requires substantially less memory capacity. The size of the BIOS image is further reduced given the prevalence of microcontrollers which have their own ROM-BIOS, such as graphic controllers and drive controllers.
Typically, flash ROM containing BIOS information may be connected to a MSIO (mobile super I/O) chip housed on an external bus or is directly linked to an external bus. While system ROM was originally housed like RAM directly off the memory controller of the computer system, it became necessary to migrate system ROM away from the 128 KB BIOS space to the external bus, allowing for extended and expanded ROM. Recently, peripheral and other units located off of the external bus are being integrated onto a primary bus such as the Peripheral Component Interconnect (PCI) bus. This has been done to eliminate an external bus and thereby optimize space within a computer system. Thus, given the reduction in the size of the BIOS image and migration of external bus units to the PCI bus, location of ROM-BIOS on the external bus is undesirable.
Moreover, flash ROM for BIOS is typically parallel-access in order to optimize the speed in communicating with flash ROM. However, ROM access times for BIOS are already largely irrelevant because of shadowing. Shadowing is the process of the CPU copying contents of selected portions of ROM-BIOS into predetermined temporary memory locations in dynamic random access memory (DRAM). The portions of the DRAM which receive the selected portion of the BIOS are sometimes referred to as the shadow RAM. Once the selected portions of ROM-BIOS are transferred, these portions of ROM-BIOS are disabled, and the corresponding portions of shadow RAM are enabled. Once shadowed, accesses to BIOS routines are accelerated because the RAM access time is much faster than the ROM access time. Furthermore, the decrease in run-time support services as a BIOS segment further reduces a concern for BIOS access times. In particular, when run-time support services are eliminated, firmware is used only to boot-strap the operating system, with the firmware no longer being needed after the operating system is loaded. Thus, given the reduced concern for BIOS access times, parallel-access ROM is an unnecessary system cost.
During boot-up, the CPU sends a read request for BIOS code at a predetermined location to the memory controller. The memory controller then addresses the parallel-access flash ROM to the mapped location corresponding to the CPU address given by the CPU and requests the code at the flash ROM address. In response to the read request by the memory controller, the flash ROM returns the line of code at the mapped location to the memory controller, and the memory controller then returns the code to the CPU. This process continues until the system is initialized or an interrupt signal is received. Given the addressing and mapping entailed in communicating with the flash ROM, flash ROM is thus accessed randomly by the memory controller during boot-up. However, random accesses to ROM are generally not favored, due to the lack of rapid implementation.